Semiconductor device and method for manufacturing same

专利摘要:
The present invention provides a semiconductor device including a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and a source-drain diffusion layer formed in the semiconductor substrate near the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film disposed on the gate electrode is thicker than the silicide film disposed on the source-drain diffusion layer. The invention also provides a method for manufacturing a semiconductor device in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, and then a source-drain diffusion layer is formed in the semiconductor substrate. Next, atoms that inhibit suicide formation are selectively introduced into the source-drain diffusion layer, and then a metal film having a high melting point is formed on each of the gate electrode and the source-drain diffusion layer. The high melting point metal film is converted into a silicide film to selectively form a silicide film on the gate electrode and the source-drain diffusion layer. This particular method retards the formation of the silicide film on the source-drain diffusion layer so that the silicide film formed on the gate electrode obtains a salicide structure semiconductor device thicker than the silicide film formed on the source-drain diffusion layer.
公开号:KR19990036745A
申请号:KR1019980041273
申请日:1998-09-30
公开日:1999-05-25
发明作者:가쯔라 미야시따；히사오 요시무라；마리꼬 다까기
申请人:니시무로 타이죠；가부시끼가이샤 도시바；
IPC主号:

专利说明:

Semiconductor device and method for manufacturing same
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductors having a MIS (metal-insulator-semiconductor) structure, and more particularly, to a semiconductor device including a metal silicide film formed to cover a gate electrode and a source-drain diffusion layer, and a method of manufacturing the same.
Recently, semiconductor devices of a CMOS (Complementary Metal Oxide Semiconductor) structure, which is a typical MIS structure, have made significant improvements in density and operation speed due to miniaturization.
As miniaturization, particularly less than 1/4 micron, increases the ratio of delays caused by parasitic components such as resistance and capacitance to transistor-specific delay components, the source-drain region is needed to achieve high speed operation of the device. And it is absolutely necessary to reduce the resistance of the gate electrode.
As a means for reducing the resistance, salicide structures are known in which a silicide film is selectively formed to cover the source-drain diffusion layer and the gate electrode.
In order to form the salicide structure, a high melting point metal such as Ti, Co, or Ni is deposited by, for example, a sputtering method on a semiconductor substrate having a source-drain diffusion layer and a gate electrode thereon, and then The substrate is annealed to selectively remove unreacted high melting point metal to convert the high melting point metal deposited on the source-drain diffusion layer and the gate electrode into silicide. As a result, a low resistivity silicide film is selectively formed on the source-drain diffusion layer and the gate electrode by self-alignment. The structure formed by a special method of forming a silicide film is called a salicide structure.
1 is a cross-sectional view illustrating the basic configuration of a field effect transistor of a MOS structure (MOS-FET) using a salicide structure. As shown in the figure, a well 108 is formed in the silicon semiconductor substrate 101. A gate electrode 103 made of polycrystalline silicon is formed on the surface of the well 108 with a gate oxide film 102 interposed therebetween. A gate sidewall film 104 composed of a silicon nitride film is formed on the side of the gate electrode 103.
In addition, a shallow source-drain diffusion layer 105 and a deep source-drain diffusion layer 106 are formed below the gate sidewall film 104. In addition, a silicide film 107 is formed on the deep source-drain diffusion layer 106 and the gate electrode 103.
The silicide film 107 is formed as follows. In particular, after the formation of the deep source-drain diffusion layer 106, a high melting point metal film is deposited to a thickness of about 30 nm on the semiconductor substrate including the deep source-drain diffusion layer 106 and the gate electrode 103. Next, an annealing treatment is applied to the metal on the deep source-drain diffusion layer 106 and the gate electrode 103 to convert the metal layer into a silicide layer, thereby selectively removing unreacted high melting point metal. As a result, the silicide film 107 is formed on the deep source-drain diffusion layer 107 and the gate electrode 103 selectively by self alignment.
In a semiconductor device employing a conventional salicide structure as shown in Fig. 1, it is essential to form a deep source-drain diffusion layer. If the source-drain diffusion layer is shallow, the silicon in the source-drain diffusion layer is consumed in the step of encapsulating the silicide in the salicide structure, resulting in leakage at the junction. Further, the ratio of the thickness of the silicon film consumed to the thickness of one unit of the metal film in the step of forming the silicide is 2.27 when forming the titanium silicide (TiSi ₂ ), and 3.64 when forming the cobalt silicide (CoSi ₂ ). And 1.83 for forming nickel silicide (NiSi).
Note that if a shallow junction is formed as a source-drain diffusion layer using a conventional silicide film, junction leakage occurs at the shallow junction. In order to prevent this junction leakage, it is essential to form a deep junction as a source-drain diffusion layer.
The problem solved by the present invention will be described.
As mentioned above, if a deep junction is formed as a source-drain diffusion layer, occurrence of short channel effects in the MOS-FET becomes significant. As a result, it becomes essential to ensure a sufficient width of the gate sidewall film that hinders miniaturization of the semiconductor device.
When the salicide structure is adopted, the contact resistance at the interface between the silicide film and the silicon layer and the resistance of the shallow junction occupy a very high proportion with respect to the overall parasitic resistance in the source-drain diffusion layer. Therefore, even if the silicide film formed on the diffusion layer is changed, the parasitic resistance is not significantly changed. If the parasitic resistance is set to about 5% of the specific resistance, it is possible to reduce the thickness of the silicide film formed on the diffusion layer even if it is necessary to reduce the parasitic resistance when miniaturizing the semiconductor device.
On the other hand, in order to achieve high speed operation, for example, it is necessary to reduce the gate delay time of the CMOS inverter. In order to achieve this object, it is necessary to form a low resistance gate electrode.
FIG. 2 shows the sheet resistance of the silicide film disposed on the gate electrode and the source-drain diffusion layer required for the gate length of each semiconductor generation.
On the other hand, if for simplicity it is assumed that the resistivity of the silicide film is not dependent on the size, that is, there is no so-called "fine wire effect", the resistivity of the silicide film does not change as the film becomes thinner. Assume that the sheet resistance of the silicide film is inversely proportional to the thickness of the silicide film. As the gate length decreases, it is necessary to increase the thickness of the silicide film disposed on the gate electrode in the future.
The object of the present invention made in view of the above situation is to make the silicide film disposed on the gate electrode thicker than the silicide film disposed on the source-drain diffusion layer so as to facilitate the miniaturization and increase the operating speed of the semiconductor device. It is to provide a semiconductor device having a salicide structure.
It is another object of the present invention to provide a method of manufacturing a semiconductor device having a salicide structure such that the silicide film disposed on the gate electrode is thicker than the silicide film disposed on the source-drain diffusion layer.
According to an aspect of the present invention for achieving the above object, a source-drain diffusion layer formed on a semiconductor substrate, a first silicide film formed on the source-drain diffusion layer, a gate formed on the gate insulating film disposed on the semiconductor substrate There is provided a semiconductor device comprising an electrode and a second silicide film disposed on the gate electrode and thicker than the first silicide film.
In a semiconductor device of a special configuration, the silicide film disposed on the gate electrode becomes thicker than the silicide film disposed on the source-drain diffusion layer, promoting miniaturization and increasing the operating speed of the semiconductor device.
According to another feature of the invention, forming a gate insulating film on the semiconductor substrate, forming a gate electrode on the gate insulating film, forming a source-drain diffusion layer on the semiconductor substrate, suppressing silicidation (silicidation) Selectively introducing atoms into the source-drain diffusion layer, forming a film of high melting point metal on the gate electrode and the source-drain diffusion layer, and selectively forming a silicide film on the gate electrode and the source-drain diffusion layer. A method for manufacturing a semiconductor device is provided, which includes converting a metal film into a silicide film.
In the method of the present invention for manufacturing a semiconductor device, atoms that inhibit suicide are selectively introduced into the source-drain diffusion layer to retard the formation of the silicide film on the source-drain diffusion layer, so that the silicide film disposed on the gate electrode is sourced. It becomes thicker than the silicide film disposed on the drain diffusion layer.
According to another feature of the invention, forming a gate insulating film on a semiconductor substrate, forming a source-drain diffusion layer on the semiconductor substrate, forming a film to suppress suicide on the source-drain diffusion layer, Forming a film of a metal having a high melting point on the gate electrode and the source-drain diffusion layer, and converting the high melting point metal into a silicide film to selectively form a silicide film on the gate electrode and the source-drain diffusion layer. Provided is a method of manufacturing a semiconductor device comprising the steps.
According to a special manufacturing method of the present invention, a film for inhibiting suicideation, for example, an oxide film is selectively formed on the source-drain diffusion layer so as to retard suicideation of the high melting point metal film disposed on the source-drain diffusion layer. . Thus, the silicide film disposed on the gate electrode may be made thicker than the silicide film disposed on the source-drain diffusion layer.
According to another feature of the invention, forming a gate insulating film on the semiconductor substrate, forming a gate electrode on the gate insulating film, forming a source-drain diffusion layer on the semiconductor substrate, the gate electrode and the Forming an insulating film on a source-drain diffusion layer, thinning the insulating film to expose a surface of the gate electrode while maintaining the state where the source-drain diffusion layer is covered with the insulating film, and the gate electrode Introducing atoms into a region near the surface of the gate electrode such that an upper portion of the gate electrode is in an amorphous state, removing the insulating layer disposed on the source-drain diffusion layer, the gate electrode and the source-drain diffusion layer Forming a metal film having a high melting point thereon, and the gate electrode and Group source - is selectively method of manufacturing a semiconductor device, comprising the step of converting the high melting point metal film to a silicide film so as to form a silicide film on a drain diffusion layer is provided.
According to the special manufacturing method of the present invention, an amorphous layer is selectively formed on top of the gate electrode to promote silicideization on top of the gate electrode. Thus, the silicide film disposed on the gate electrode may be made thicker than the silicide film disposed on the source-drain diffusion layer.
According to another feature of the invention, forming a gate insulating film on a semiconductor substrate, forming an amorphous silicon film having a form of a gate electrode on the gate insulating film, forming a source-drain diffusion layer on the semiconductor substrate Forming a metal film having a high melting point on the amorphous silicon film and the source-drain diffusion layer, and selectively forming a silicide film on the amorphous silicon film and the source-drain diffusion layer as a silicide film. A semiconductor device manufacturing method is provided that includes converting.
According to the special manufacturing method of the present invention, the gate electrode is formed by using amorphous silicon. As a result, the silicide formation rate on the gate electrode is promoted such that the silicide film disposed on the gate electrode is thicker than the silicide film disposed on the source-drain diffusion layer.
According to another feature of the invention, forming a gate insulating film on the semiconductor substrate, forming a gate electrode on the gate insulating film, forming a source-drain diffusion layer on the semiconductor substrate, the gate electrode and the Selectively forming a silicide film on a source-drain diffusion layer, forming an insulating film on the gate electrode and the silicide film disposed on the source-drain diffusion layer,
Thinning the insulating film to expose the silicide film disposed on the gate electrode while keeping the silicide film disposed on the source-drain diffusion layer covered with the insulating film, and on the surface of the exposed silicide film There is provided a semiconductor device manufacturing method comprising the step of further forming a silicide film.
In the special manufacturing method of the present invention, the silicide film is formed by a known method, and then the entire surface of the semiconductor substrate is covered with an insulating film. Next, the surface of the silicide film disposed on the gate electrode is exposed to the outside intensively, and then a silicide film is further selectively formed on the exposed silicide film disposed on the gate electrode. As a result, the silicide film disposed on the gate electrode is made thicker than the silicide film disposed on the source-drain diffusion layer.
Further, according to another feature of the invention, forming a gate insulating film on the semiconductor substrate, forming a gate electrode on the gate insulating film, forming a source-drain diffusion layer on the semiconductor substrate, the gate electrode And forming a metal film having a high melting point on the source-drain diffusion layer, converting the high melting point metal into a silicide film to selectively form a silicide film on the gate electrode and the source-drain diffusion layer, and the gate electrode And forming an insulating film on the silicide film disposed on the source-drain diffusion layer, wherein the silicide film disposed on the source-drain diffusion layer is covered with the insulating film while being disposed on the gate electrode. The insulation to expose the surface of the silicide film Thinning the metal, forming a high melting point metal film on the silicide film disposed on the gate electrode, and selectively forming a silicide film on the silicide film previously formed on the gate electrode. A semiconductor device manufacturing method comprising converting to a silicide film is provided.
In a special method of the present invention, a silicide film is formed using a known method, and then the entire surface of the semiconductor substrate is covered with an insulating film. Next, the surface of the silicide film disposed on the gate electrode is selectively exposed to the outside, and then a silicide film is further selectively formed on the silicide film previously formed on the gate electrode. Thus, the silicide film disposed on the gate electrode may be made thicker than the silicide film disposed on the source-drain diffusion layer.
Additional objects and advantages of the invention are set forth in the following, which may be apparent from the description, or may be learned by practice of the invention. The objects and advantages of the present invention can be realized and obtained by means and combinations particularly pointed out below.
1 is a cross-sectional view illustrating the basic configuration of a semiconductor device having a MOS structure using salicide technology.
FIG. 2 is a graph showing the sheet resistance of the source-drain diffusion layer and the silicide film disposed on the gate electrode required for the gate length for each semiconductor generation.
3 is a graph showing the thickness of the silicide film disposed on the source electrode and the drain diffusion layer and the gate electrode required for the gate length for each semiconductor generation.
4 is a cross-sectional view showing a configuration of a semiconductor device having a salicide structure according to the first embodiment of the present invention.
FIG. 5 is a graph showing the effect of gate electrode resistance on gate delay time in a semiconductor device of 0.25 [mu] m generation. FIG.
6 is a cross-sectional view showing a semiconductor device having a salicide structure according to a modification of the first embodiment of the present invention.
FIG. 7 is a cross-sectional view showing steps included in a method of manufacturing a semiconductor device having a salicide structure shown in FIG. 4 according to a second embodiment of the present invention;
FIG. 8 is a cross-sectional view showing other steps included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the second embodiment of the present invention. FIG.
9 is a cross-sectional view showing yet another step included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the second embodiment of the present invention.
FIG. 10 is a cross-sectional view showing further steps included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the second embodiment of the present invention. FIG.
FIG. 11 is a cross-sectional view showing further steps included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the second embodiment of the present invention. FIG.
12 is a cross-sectional view showing yet another step included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the second embodiment of the present invention.
FIG. 13 is a cross-sectional view showing steps included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 6 according to the third embodiment of the present invention. FIG.
FIG. 14 is a cross-sectional view showing other steps included in the semiconductor device manufacturing method having the salicide structure shown in FIG. 6 according to the third embodiment of the present invention. FIG.
FIG. 15 is a sectional view showing yet another step included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 6 according to the third embodiment of the present invention; FIG.
FIG. 16 is a cross-sectional view showing yet another step included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 6 according to the third embodiment of the present invention. FIG.
FIG. 17 is a cross-sectional view showing further steps included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 6 according to the third embodiment of the present invention. FIG.
FIG. 18 is a sectional view showing yet another step included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 6 according to the third embodiment of the present invention; FIG.
FIG. 19 is a cross-sectional view showing steps included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the fourth embodiment of the present invention. FIG.
20 is a cross-sectional view showing other steps included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the fourth embodiment of the present invention.
FIG. 21 is a sectional view showing yet another step included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the fourth embodiment of the present invention; FIG.
FIG. 22 is a cross-sectional view showing further steps included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the fourth embodiment of the present invention. FIG.
FIG. 23 is a cross-sectional view showing further steps included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the fourth embodiment of the present invention. FIG.
FIG. 24 is a sectional view showing yet another step included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the fourth embodiment of the present invention; FIG.
FIG. 25 is a cross-sectional view showing the steps involved in the manufacturing method of the semiconductor device having the salicide structure shown in FIG. 4 according to the fifth embodiment of the present invention; FIG.
FIG. 26 is a cross-sectional view showing other steps included in the semiconductor device manufacturing method having the salicide structure shown in FIG. 4 according to the fifth embodiment of the present invention; FIG.
FIG. 27 is a sectional view showing yet another step included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the fifth embodiment of the present invention; FIG.
FIG. 28 is a cross-sectional view showing steps included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the sixth embodiment of the present invention. FIG.
FIG. 29 is a cross-sectional view showing other steps included in the semiconductor device manufacturing method having the salicide structure shown in FIG. 4 according to the sixth embodiment of the present invention. FIG.
30 is a cross-sectional view showing yet another step included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the sixth embodiment of the present invention.
FIG. 31 is a sectional view showing yet another step included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the sixth embodiment of the present invention; FIG.
32 is a cross-sectional view showing yet another step included in the method for manufacturing a semiconductor device having the salicide structure shown in FIG. 4 according to the sixth embodiment of the present invention.
<Explanation of symbols for main parts of the drawings>
2: semiconductor substrate
4: device isolation region
6: well
8: gate insulating film
10: polycrystalline silicon film
12, 20: silicide film
14: gate sidewall film
16: shallow diffusion layer
18: deep diffusion layer
BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate preferred embodiments of the invention and, together with the foregoing general description and the following detailed description of the preferred embodiments, serve to explain the principles of the invention. do.
Some embodiments of the invention are described with reference to the accompanying drawings.
(First embodiment)
As a first embodiment of the present invention, a semiconductor device having a salicide structure will be described.
In particular, FIG. 4 is a cross-sectional view showing the configuration of a semiconductor device having a salicide structure. As shown in the figure, an element isolation region 4 is formed on the semiconductor substrate 2, and a well 6 is formed in an element formation region defined between two adjacent element isolation regions 4. Further, a gate insulating film 8 made of a silicon oxide film is formed in the active element region included in the element formation region.
A gate electrode having a polyside form composed of the polycrystalline silicon film 10 and the silicide film 12 formed on the polycrystalline silicon film 10 is formed on the gate insulating film 8. The silicide film 12 is made of, for example, a titanium silicide (TiSi ₂ ) film, a cobalt silicide (CoSi ₂ ) film, or a nickel silicide (NiSi) film. In addition, gate sidewall films 14 each formed of a silicon nitride film are formed on both sidewalls of the gate electrode.
A shallow diffusion layer 16 serving as a source or drain region is formed in the well 6 so as to be disposed under the gate sidewall film 14. In addition, a deep diffusion layer 18 serving as a source or drain region is formed outside the diffusion layer 16 that is shallow to the gate electrode. The silicide film 20 is composed of, for example, a titanium silicide (TiSi ₂ ) film, a cobalt silicide (CoSi ₂ ) film, or a nickel silicide (NiSi) film.
In the above-described semiconductor device having the salicide structure, the silicide film 12 formed on the polycrystalline silicon film 10 included in the gate electrode has at least the silicide film formed on the deep diffusion layer 18 constituting the source or drain region. It has a thickness of 1.2 times, preferably twice the thickness of 20). For example, the thickness of the silicide film 12 included in the gate electrode is set to 60 nm or more, and the thickness of the silicide film 20 formed on the deep diffusion layer 18 is set to 50 nm or less.
The reason why the silicide film 12 included in the gate electrode is at least 1.2 times as thick as the silicide film 20 disposed on the deep diffusion layer 18 is as follows.
In particular, FIG. 5 is a graph showing the influence of the gate electrode resistance on the gate delay time in the semiconductor generation of 0.25 μm calculated using the “Sakurai model”. The plotting on the abscissa of the graph is the thickness ratio of the silicide film included in the gate electrode to the silicide film disposed on the source-drain diffusion layer, that is, Tg / Tsg, and the resistance of the silicide film disposed on the source-drain diffusion layer is 100 [Ω]. / sq.].
On the other hand, the plotting on the ordinate of the graph is the gate delay time drop (Δτpd / τpd). "Gate delay time drop" refers to the deterioration rate of the intrinsic gate delay time of a transistor due to gate electrode resistance. The calculation conditions are as follows: Δτpd / τpd = (1/3) × (Rg × Cg / τpd) ² , τpd = 30 ps, Cg = L × W × 6 fF / μm ² , w = 15 μm, L = 0.25 μm, psd = 10 μs / sq.
It is assumed in circuit design that the maximum channel width W is set to, for example, 15 μm. In this case, in order to suppress the degradation caused by the gate electrode resistance to 5% (0.05) or less, it is understood that the silicide film included in the gate electrode should be at least 1.2 times thicker than the silicide film disposed on the source-drain diffusion layer. Can be.
A related "Sakurai model" is described by T. Sakurai and T. Iizuka's 'Gate Electrode RC Delay Effects in VLSI', IEEE Trans. on ED, ED-32, 2, February 1985, pp. 370-374.
In the first embodiment of the present invention, the silicide layer 12 and the silicide layer 20 may be any one of a titanium silicide layer, a cobalt silicide layer, and a nickel silicide layer as described above. These silicide films 12 and 20 may be made of a silicide of a metal having a high melting point.
The gate insulating film 8 is made of a silicon oxide film in the above-described embodiment. As another method, an insulating film such as a silicon nitride film or a silicon nitride oxide film may be used as the gate insulating film 8. The silicon semiconductor substrate 2 may be p-type or n-type.
As described above, in the first embodiment of the present invention, the silicide film 12 included in the gate electrode is formed thicker than the film widely used in the conventional semiconductor device. In addition, the silicide film 20 disposed on the source-drain diffusion layer is formed thinner than the film widely used in the conventional semiconductor device. Note that in the semiconductor device according to the first embodiment of the present invention, the silicide film 12 includes a salicide structure that is at least 1.2 times thicker than the silicide film 20. The special arrangement used in the first embodiment of the present invention makes it possible to suppress current leakage at the junction of the shallow source-drain diffusion layer while lowering the resistance of the gate electrode.
Next, another semiconductor device having a salicide structure will be described as a modification of the first embodiment of the present invention.
Specifically, FIG. 6 shows a configuration of a semiconductor device having a salicide structure, which is an example of the first embodiment of the present invention. In the first embodiment shown in Fig. 4, the gate sidewall film 14 formed to cover both side surfaces of the gate electrode is made of a silicon nitride film. However, in the modification shown in FIG. 6, the gate sidewall film 22 made of the silicon oxide film is formed instead of the gate sidewall film 14 made of the silicon nitride film. The remaining parts of the semiconductor device shown in FIG. 6 are the same as the device shown in FIG. Therefore, the same reference numerals are assigned to the same parts in FIGS. 4 and 6, and description thereof will be omitted.
In the modification shown in FIG. 6, the silicide film 12 included in the gate electrode is formed thicker than the film widely used in the conventional semiconductor device. In addition, the silicide film 20 disposed on the source-drain diffusion layer is formed thinner than the film widely used in the conventional semiconductor device. In the semiconductor device according to the modification shown in FIG. 6, it is noted that the silicide film 12 includes a salicide structure that is at least 1.2 times thicker than the silicide film 20. The special construction used in this variant makes it possible to suppress the current leakage at the junction of the shallow source-drain diffusion layer while lowering the resistance of the gate electrode. In addition, it is possible to provide a small MIS transistor capable of high speed operation.
In this variant, it is assumed in circuit design that the maximum channel width W is set to, for example, 15 μm. In this case, similarly to the first embodiment, in order to suppress the deterioration caused by the gate electrode resistance to 5% (0.05) or less, the silicide film 12 included in the gate electrode is silicide disposed on the source-drain diffusion layer. It can be seen that it should be at least 1.2 times thicker than the membrane 20. Therefore, the silicide film 12 included in the gate electrode is formed at least 1.2 times thicker than the silicide film 20 disposed on the source-drain diffusion layer.
(2nd Example)
As a second embodiment of the present invention, a method of manufacturing the semiconductor device of the first embodiment of the present invention shown in Fig. 4 having a salicide structure will be described. In the second embodiment, each of the silicide films 12 and 20 is made of titanium silicide. The silicon semiconductor substrate 20 is p-type.
7 to 12 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention. In the method of the second embodiment of the present invention, a semiconductor device according to the first embodiment of the present invention having a salicide structure and shown in Fig. 4 is manufactured.
In the first step, the element isolation region 4 is formed on the p-type silicon semiconductor substrate 2A to a depth of about 300 nm by the buried element isolation method as shown in FIG. Subsequently, a buffer oxide film is formed to a thickness of about 10 nm on the p-type silicon semiconductor substrate 2A in the element formation region disposed between the adjacent element isolation regions 4.
After formation of the buffer oxide film, n well 6, p well 24 and channel are formed in the element formation region on p-type silicon semiconductor substrate 2A by ion implantation. Ion implantation is done under conventional conditions used to form these regions. For example, to form the n-type well 6, phosphorus ions P ⁻ are implanted at a dose of 3 × 10 ¹³ cm ⁻² under an acceleration energy of 500 keV. In order to form the channel region of the n-type well 6, boron ions B ⁺ are implanted at a dose of 1.5x10 ¹³ cm ^-2 under an acceleration energy of 50 keV. In order to form the p-type well 24, boron ions B ⁺ are implanted at a dose of 2 x 10 ¹³ cm ^-2 under an acceleration energy of 260 keV. In order to form the channel region of the p-type well 24, phosphorus ions P ⁻ are implanted at a dose of 1.0 × 10 ¹³ cm ⁻² under an acceleration energy of 130 keV.
After the ion implantation step, the buffer oxide film is removed and a gate oxide film 8 made of a silicon oxide film having a thickness of 2.5 nm to 6.0 nm is formed by thermal oxidation method or LPCVD method. Next, the polycrystalline silicon film 10 for forming the gate electrode is formed on the gate insulating film 8 by the LPCVD method with a thickness of 200 nm, and then the protective film of the gate electrode with a thickness of 30 nm by the LPCVD method, for example. A silicon oxide film 26 acting as a film is formed.
After the silicon oxide film 26 is applied to the photoresist film, the photoresist film is patterned by a photolithography method, an X-ray lithography method or an electron beam exposure method, and the silicon oxide film 26 by a reactive ion etching (RIE) method. The polycrystalline silicon film 10 is etched to form a gate electrode.
In addition, shallow diffusion layers 16 and 28 serving as source and drain regions are formed by ion implantation to provide the structure shown in FIG. Ion implantation is performed under conventional conditions. For example, to form a shallow diffusion layer 16, and implanting BF ₂ ⁺ ion as a dose under the acceleration energy of 10 keV 5.0 × 10 ¹⁴ ㎝ ^-2. On the other hand, in order to form the shallow diffusion layer 28, arsenic ions (As ⁺ ) ions are implanted at a dose of 5.0 x 10 ¹⁴ cm ^-2 under an acceleration energy of 15 keV.
In the next step, as shown in Fig. 8, a silicon nitride film is deposited on the entire surface of the p-type silicon semiconductor substrate 2A by the LPCVD method, and anisotropically etched the silicon nitride film by the RIE method to the side of the gate electrode. The gate sidewall film 14 is formed. Subsequently, deep diffusion layers 18 and 30 are formed in the n-type well 6 and the p-type well 24 by ion implantation. Ion implantation is performed under conventional conditions. For example, deep in order to form the diffusion layers 18, BF ₂ ⁺ ions are implanted with a dose under a 30 keV acceleration energy of 4.0 × 10 ¹⁴ ㎝ ^-2. On the other hand, in order to form the deep diffusion layer 30, arsenic ions (As ⁺ ) ions are implanted at a dose of 4.0 x 10 ¹⁵ cm ^-2 under an acceleration energy of 50 keV.
In the ion implantation step, the polycrystalline silicon film 10 serving as the gate electrode is also doped with impurities through the silicon oxide film 26. Thus, the doped impurities are activated by an activation annealing treatment by RTA, so that each of the deep diffusion layers 18 and 30 and the polycrystalline silicon film 10 forming the gate electrode are at least 1.0 × 10 ²⁰ cm ⁻³ It has an impurity concentration. 8 shows the structure after the ion implantation step to form the deep diffusion layers 18, 30.
In the next step, fluorine ions are implanted into the surface regions 18a and 30a of the deep diffusion layers 18 and 30, respectively, under low acceleration energy. In this step, nitrogen ions or oxygen ions may be implanted instead of fluorine ions. Ion implantation is carried out with a dose of about 1.0 × 10 ¹⁴ to 1.0 × 10 ¹⁵ cm ^-2 under an acceleration energy of 3 to 10 keV. The gate oxide film 8 disposed on the deep diffusion layers 18 and 30 is removed or remarkably thinned by anisotropic etching in the step of forming the gate sidewall film 14, thereby forming the surface regions 18a and 30a. Note that the fluorine ion implantation is not inhibited by the gate oxide film 8. On the other hand, since the polycrystalline silicon film 10 is covered with the silicon oxide film 26, fluorine ions are not implanted into the polycrystalline silicon film 10 forming the gate electrode.
It is known in the art that fluorine, nitrogen and oxygen atoms contained in the silicon layer inhibit silicideization of the silicon layer. The fluorine, nitrogen and oxygen atoms implanted into the surface regions 18a and 30a of the deep diffusion layers 18 and 30 are then transferred into the surface region 18a of the deep diffusion layer 18 and the surface region 30a of the deep diffusion layer 30. It serves to hinder the formation of the silicide film carried out in the step of. FIG. 9 shows the structure after the surface regions 18a and 30a of the deep diffusion layers 18 and 30 are formed, respectively.
In the next step, the silicon oxide film 26 serving as the protective film of the gate electrode is removed by wet etching, as shown in FIG. Then, the titanium layer 32 is formed to a thickness of 40 nm on the entire surface by the sputtering method, as shown in FIG. 11, and then heat treated by RTA at 700 ° C. for 30 seconds. By this heat treatment, the titanium layer disposed on the polycrystalline silicon film 10 serving as the gate electrode and the deep diffusion layers 18 and 30 is converted into a titanium silicide layer. The unreacted titanium is then treated with a mixed solution consisting of sulfuric acid and hydrogen peroxide and selectively removed, as shown in FIG. 12, followed by a heat treatment by RTC at 850 ° C. for 20 seconds. As a result, titanium silicide films 12 and 20 are selectively formed on the polycrystalline silicon film 10 serving as the gate electrode and in the surface regions 18a and 30a of the deep diffusion layers 18 and 30, respectively.
As described above, the fluorine atoms that suppress the silicideation of the metal, in order to lower the formation rate of the titanium silicide film 20 in the surface regions 18a and 30a, the surface regions 18a of the deep diffusion layers 18 and 30. And 30a), respectively. On the other hand, since the suicide of the titanium layer disposed on the polycrystalline silicon film 10 is not suppressed, the titanium silicide film 12 is formed on the polycrystalline silicon film 10 at a normal formation speed. This allows the titanium silicide film 12 disposed on the polycrystalline silicon film 10 to have a thickness 1.2 times thicker than the thickness of the titanium silicide film 20 disposed on the deep diffusion layers 18 and 30.
The semiconductor device having the salicide structure according to the first embodiment of the present invention shown in FIG. 4 may be prepared by the above-described steps. Incidentally, general fabrication processes of MOS-FETs can be used in later steps of fabricating a semiconductor device.
As described above, in the second embodiment of the present invention, atoms that inhibit silicide are selectively implanted into the source-drain diffusion layer only to prevent formation of the silicide film on the source-drain diffusion layer, and on the source-drain diffusion layer The disposed silicide film makes it possible to provide a semiconductor device having a salicide structure thinner than the silicide film disposed on the gate electrode. As described above, in the present invention, it is important that the silicide film disposed on the gate electrode is at least 1.2 times thicker than the silicide film disposed on the source-drain diffusion layer.
In the second embodiment described above, each of the silicide film 12 included in the gate electrode and the silicide film 20 disposed on the source-drain diffusion layer is made of titanium silicide. However, these silicide films need not be limited to titanium silicide films. In particular, these silicide films may be composed of silicides of metals having high melting points such as cobalt and nickel.
Further, the gate insulating film 8 is composed of a silicon oxide film in the above-described second embodiment. However, other insulating films such as other silicon nitride films or silicon oxynitride films may be used instead of the silicon oxide films forming the gate insulating film 8. Also, a p-type silicon semiconductor substrate is used in the second embodiment described above. However, n-type silicon semiconductor substrates may also be used.
(Third Embodiment)
A third embodiment of the present invention relates to the manufacture of a semiconductor device having the salicide structure shown in Fig. 6, which is a modification of the semiconductor device according to the first embodiment of the present invention. In the third embodiment, the silicide films 12 and 20 are composed of titanium silicide films as in the second embodiment. In addition, the semiconductor silicon substrate 2A used in the third embodiment becomes a p-type conductor.
13 to 18 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention. The third embodiment shows the manufacture of a semiconductor device having the salicide structure shown in Fig. 6, which is a modification of the semiconductor device according to the first embodiment of the present invention.
In the first step, the device isolation region 4 is formed on the p-type silicon semiconductor substrate 2A with a depth of about 300 nm by a buried device isolation method as shown in FIG. 13 as in the second embodiment. do. A buffer oxide film is then formed to a thickness of about 10 nm on the surface of the p-type silicon semiconductor substrate 2A in the element formation region disposed between two adjacent element isolation regions 4.
After the buffer oxide film is formed, the n-type well 6, the p-type well 24 and the channel region are formed in the element formation region on the p-type silicon semiconductor substrate 2A by ion implantation. Ion implantation is performed under general conditions as in the second embodiment. Then, the buffer oxide film is removed, and then a gate insulating film 8 made of a silicon oxide film having a thickness of 2.5 nm to 6.0 nm is formed by thermal oxidation method or LPCVD method. In addition, a polycrystalline silicon film 10 acting as a gate electrode is formed by the LPCVD method on the gate insulating film 8, and then a silicon nitride film 40 acting to protect the gate electrode is 30 by the LPCVD method, for example. It is formed to a nm thickness.
Thus, the silicon nitride film 40 is coated with a photoresist film, and then the photoresist film is patterned by photolithography, X-ray lithography or electron beam exposure. Then, the silicon nitride film 40 and the polycrystalline silicon film 10 are etched by reactive ion etching (RIE) to form a gate electrode.
After the formation of the gate electrode, thin diffusion layers 16 and 28 which operate as source-drain regions are formed in the n-type well 6 and the p-type well 24 by ion implantation, respectively. Ion implantation is performed under general conditions, as in the second embodiment. 13 shows the resulting structure.
In the next step, a silicon oxide film is deposited on the entire surface of the p-type silicon semiconductor substrate 2A by LPCVD, and then a gate sidewall film 22 is formed on the side of the gate electrode as shown in FIG. Anisotropic etching is applied to the silicon oxide film by the RIE method. Then, deep diffusion layers 18 and 30 which operate as source-drain regions are formed in the n-type well 6 and the p-type well 24 by ion implantation methods, respectively. Ion implantation is performed under general conditions, as in the second embodiment.
It should be noted that the polycrystalline silicon film 10 acting as the gate electrode is also doped with impurities through the silicon nitride film 40 in the ion implantation step of forming the deep diffusion layers 18 and 30. Thus, the doped impurities are activated by an activation annealing treatment by RTA, so that each of the deep diffusion layers 18 and 30 and the polycrystalline silicon film 10 acting as the gate electrode is at least 1.0 × 10 ²⁰ cm ⁻³ . It can have a concentration. 14 shows the resulting structure.
In the next step, as shown in Fig. 15, a silicon myth film 42 is formed on the deep diffusion layers 18 and 30 in a thickness of 3.0 nm to 5.0 nm by thermal oxidation or chemical oxidation. Then, the silicon nitride film 40 operating to protect the gate electrode is removed by wet etching using, for example, heated phosphoric acid, as shown in FIG. Under these conditions, only traces of the native oxide film are present on the polycrystalline silicon oxide film 10 serving as the gate electrode. On the other hand, the silicon oxide film 42 remains on the diffusion layers 18 and 30 without being removed.
Further, as shown in Fig. 17, the titanium layer 44 is deposited to a thickness of 40 nm on the entire surface by sputtering, followed by heat treatment by RTA at 700 DEG C for about 30 seconds. By this heat treatment, the polycrystalline silicon film 10 serving as the gate electrode and the titanium layer disposed on the deep diffusion layers 18 and 30 are converted into a titanium silicide film. Then, as shown in Fig. 18, the unreacted titanium film is selectively removed by a selective removal method using a mixed solution containing sulfuric acid and hydrogen peroxide, followed by heat treatment by RTA for 20 seconds at 850 ° C. As a result, titanium silicide films 12 and 20 are selectively formed on the polycrystalline silicon film 10 and the deep diffusion layers 18 and 30, respectively, serving as gate electrodes alone.
As described above, a thick silicon oxide film 42 is formed on the deep diffusion layers 18 and 30, with the result that the titanium layer 44 is consumed to some extent for the reduction of oxygen contained in the silicon oxide film 42. . This allows the titanium silicide film 20 to be formed at low temperatures on the deep diffusion layers 18 and 30. On the other hand, silicidation of the titanium layer 44 formed on the polycrystalline silicide layer 10 is not suppressed, and as a result, the titanium silicide film 12 is formed under general conditions. In conclusion, the titanium silicide film 12 formed on the polycrystalline silicon film 10 has a thickness at least 1.2 times thicker than the thickness of the titanium silicide film 20 formed on the deep diffusion layers 18 and 30.
A semiconductor device having the salicide structure shown in Fig. 6, which is a modification of the semiconductor device according to the first embodiment, is prepared by the steps described above. Incidentally, the general fabrication process of the MOS-FET can be used in subsequent fabrication steps of the semiconductor device.
As described above, according to the third embodiment of the present invention, an oxide film is selectively formed on the source-drain diffusion layer alone. As a result, the titanium layer disposed on the oxide film is partially consumed for the reduction of oxygen contained in the oxide film to prevent the formation of the titanium silicide film on the source-drain diffusion layer. This makes it possible to provide a device with a salicide structure semiconductor structure in which the silicide film formed on the gate electrode is thicker than the silicide film formed on the source-drain diffusion layer. It should be noted that the silicide film formed on the gate electrode is 1.2 times thicker than the silicide film formed on the source-drain diffusion layer.
Conversely, this makes it possible to use a silicon nitride film for forming a silicon oxide film on the polycrystalline silicon film 10 serving as a gate electrode and for forming the gate sidewall film 22. In this case, the silicon nitride film formed on the polycrystalline silicon film 10 is formed on the deep diffusion layers 18 and 30 so that the silicon nitride film can be used on the deep diffusion layers 18 and 30 as a film for suppressing suicide of the titanium layer. After the silicon nitride film is formed in the film, the silicon nitride film is removed by wet etching.
In the third embodiment described above, each of the silicide film 12 included in the gate electrode and the silicide film 20 disposed on the source-drain diffusion layer is made of titanium silicide. However, these silicide films need not be limited to titanium silicide films. In particular, these silicide films may be composed of silicides of metals having high melting points such as cobalt and nickel.
Note that the gate insulating film 8 is composed of a silicon oxide film in the third embodiment described above. However, another insulating film such as a silicon nitride film or a silicon nitride oxide film can be used in place of the silicon oxide film for forming the gate insulating film 8. Also, a p-type silicon semiconductor substrate can be used in the above-described second embodiment. However, n-type silicon semiconductor substrates may also be used.
(Example 4)
A fourth embodiment of the present invention shows the manufacture of a semiconductor device having the salicide structure shown in Fig. 4 which is a semiconductor device according to the first embodiment of the present invention. In the fourth embodiment, the silicide films 12 and 20 are made of a titanium silicide film as in the second embodiment. In addition, the silicon semiconductor substrate 2A used in the fourth embodiment becomes a p-type conductor.
19 to 24 are cross-sectional views collectively showing a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention. The fourth embodiment shows the manufacture of a semiconductor device having the salicide structure shown in Fig. 4, which is the semiconductor device according to the first embodiment of the present invention.
In the first step, the device isolation region 4 is formed on the p-type silicon semiconductor substrate 2A by a buried device isolation method as shown in FIG. 19 to a depth of about 300 nm as in the second embodiment. Is formed. A buffer oxide film is then formed to a thickness of about 10 nm on the surface of the p-type silicon semiconductor substrate 2A in the element formation region disposed between the two adjacent element isolation regions 4.
After formation of the buffer oxide film, n-type well 6, p-type well 24 and channel regions are formed by ion implantation into the element formation region on p-type silicon semiconductor substrate 2A. As in the second embodiment, implantation of ions is carried out under normal conditions. Subsequently, the buffer oxide film is removed, and then a gate insulating film 8 made of a silicon oxide film having a thickness of 2.5 nm or 6.0 nm is formed by a thermal oxidation method or an LPCVD method. In addition, a polycrystalline silicon film 10 serving as a gate electrode is formed on the gate insulating film 10 with a thickness of 200 nm by the LPCVD method.
The polycrystalline silicon film 10 thus formed is covered with a photoresist film, and then the photoresist film is patterned by photolithography, X-ray lithography, or electron beam exposure. Next, the polycrystalline silicon film 10 is etched by a reactive ion etching (RIE) method to form a gate electrode.
After forming the gate electrode, a thin diffusion layer serving as a source-drain region is formed in each of the n-type wells 16 and the p-type wells 24 by an ion implantation method. Ion implantation is performed under normal conditions as in the second embodiment.
In the next step, a silicon nitride film is deposited on the entire surface of the P-type silicon semiconductor substrate 2A by the LPCVD method, and then anisotropic etching is applied to the silicon nitride film by the RIE method, so that the gate sidewall film 14 is formed on the side of the gate electrode. ). Subsequently, deep diffusion layers 18 and 30 serving as source-drain regions are formed in the n-type well 6 and the p-type well 24 by ion implantation methods. The ion implantation method is performed under ordinary conditions as in the second embodiment.
It should be noted that ion implantation is directly applied to the polycrystalline silicon film 10 serving as the gate electrode, so that the polycrystalline silicon film 10 is doped to a high impurity concentration. Therefore, the doped impurities are activated by an active annealing treatment by RTA, so that each of the deep diffusion layers 18 and 30 and the polycrystalline silicon film 10 serving as the gate electrode is at least 1.0 × 10 ²⁰ cm ^-3 . Will have a concentration. 19 shows a corresponding structure.
In the next step, an insulating film 50 made of, for example, BPSG is formed on the entire surface with a thickness of about 600 nm by the LPCVD method, as shown in FIG. Subsequently, after the surface of the insulating film 50 is flattened by CMP (chemical mechanical polishing), etching back is performed together with the polycrystalline silicon film 10 used as a stopper. As a result, the surface of the polycrystalline silicon film 10 is selectively exposed to the surface as shown in FIG.
In the next step, as shown in Fig. 22, germanium ions are selectively implanted into the surface region of the polycrystalline silicon film 10 serving as the gate electrode by an ion implantation method performed under low acceleration energy. Incidentally, boron, silicon, arsenic or antimony ions may be implanted instead of germanium ions. Ion implantation in this step is carried out with a dose of about 1.0 x 10 ¹⁴ to 1.0 x 10 ¹⁵ cm ^-2 under an acceleration energy of 3 to 10 kev. As a result, the surface region of the polycrystalline silicon film 10 becomes amorphous to form the amorphous layer 52. Note that the region other than the polycrystalline silicon region 10 is covered with the insulating film 50, so that germanium ions are not implanted into the specific region.
In the prior art, it is known that silicidation of metals is promoted when the silicon layer has an amorphous surface. The amorphous surface layer 52 formed on the polycrystalline silicon film 10 serving as the gate electrode can promote the formation of the silicide film on the polycrystalline silicon film 10 in a subsequent step. 22 shows the final structure of the semiconductor device.
As shown in FIG. 23, the insulating film 50 is removed in a subsequent step by wet etching using ammonium fluoride. Note that heat treatment is not performed after the formation of the amorphous surface layer 52, so that the surface region of the polycrystalline silicon film 10 is maintained in an amorphous state.
In the next step, a titanium layer is deposited by a sputtering method on the entire surface including the polycrystalline silicon film 10 by a sputtering method, and thereafter, heat treatment is performed by RTA at 700 ° C for 30 seconds. By this heat treatment, the titanium layer disposed on the polycrystalline silicon film 10 and the deep diffusion layers 18 and 30 serving as the gate electrode is transformed into a titanium silicide film. The unreacted titanium layer is then selectively removed by a selective removal method using a mixed solution consisting of sulfuric acid and hydrogen peroxide. Thereafter, heat treatment is performed by RTA at 850 ° C. for 20 seconds. As a result, titanium silicide films 12 and 20 are selectively formed in each of the polycrystalline silicon film 10 and the deep diffusion layers 18 and 30 serving as gate electrodes.
It should be noted that as described above, the polycrystalline silicon film 10 serving as the gate electrode includes an amorphous surface layer 52 to promote the formation of the titanium silicide film 12 on the polycrystalline silicon film 10. to be. On the other hand, silicidation of the titanium layers located in the deep diffusion layers 18 and 30 is not particularly promoted. On the other hand, the titanium silicide film 20 located in the deep diffusion layers 18 and 30 is formed at a normal ratio. The titanium silicide film 12 located on the polycrystalline silicon film 10 is formed at least 1.2 times the same thickness as the titanium silicide film 20 located on the deep diffusion layers 18 and 20.
The semiconductor device having the silicide structure of the semiconductor device according to the first embodiment of the present invention shown in Fig. 4 is manufactured by the above-described steps. Incidentally, a conventional manufacturing process of the MOS-FET can be used in subsequent steps of manufacturing a semiconductor device.
As described above, according to the fourth embodiment of the present invention, an amorphous layer is selectively formed in the upper surface region of the polycrystalline silicon film 10 serving as the gate electrode so as to promote silicideization on only the gate electrode. As a result, it is possible to manufacture a semiconductor device having a silicide structure, in which the silicide film formed on the gate electrode becomes thicker than the silicide film formed on the source-drain diffusion region. More specifically, the silicide film formed on the gate electrode is at least 1.2 times the same thickness as the silicide film formed on the source-drain diffusion layer.
In the fourth embodiment described above, each of the silicide film 12 included in the gate electrode and the silicide film 20 disposed in the source-drain diffusion layer is made of titanium silicide. However, these silicide films need not be limited to titanium silicide films. Specifically, it is possible to constitute a silicide of a metal having a high melting point such as cobalt or nickel as these silicide films.
In addition, the gate insulating film 8 is comprised from the silicon oxide film in 4th Example mentioned above. However, another insulating film such as a silicon nitride film or a silicon nitrate film may be used in place of the silicon oxide film for forming the gate insulating film 8. In addition, a p-type silicon semiconductor substrate is used in the above-described second embodiment. However, it is possible to use an n-type silicon substrate.
(Example 5)
A fifth embodiment of the present invention relates to the manufacture of a semiconductor device having the salicide structure of the semiconductor device according to the first embodiment of the present invention shown in FIG. In the fifth embodiment, the silicide films 12 and 20 are composed of titanium silicide films as in the second embodiment. In addition, the silicon semiconductor substrate 2A used in the fifth embodiment is of p-type conductivity type.
25 to 27 are cross-sectional views schematically showing a method of manufacturing a semiconductor device according to the fifth embodiment of the present invention. The fifth embodiment relates to the manufacture of a semiconductor device having the salicide structure of the semiconductor device according to the first embodiment of the present invention shown in FIG.
In the first step, an element isolation region 4 is formed on the p-type silicon semiconductor substrate 2A with a depth of about 300 nm by the buried element isolation method shown in FIG. 25 as in the second embodiment. A buffer oxide film is then formed on the surface of the p-type silicon semiconductor substrate 2A in the element formation region disposed between two adjacent element isolation regions 4 with a thickness of about 10 nm.
After the formation of the buffer oxide film, the n-type well 6, the p-type well 24 and the channel region are formed by ion implantation in the element formation region on the p-type silicon semiconductor substrate 2A. Ion implantation is carried out under ordinary conditions as in the second embodiment. Subsequently, the buffer oxide film is removed, and then a gate insulating film 8 made of a silicon oxide film having a thickness of 2.5 nm to 6.0 nm is formed by a thermal oxidation method or an LPCVD method. In addition, an amorphous silicon film 60 serving as a gate electrode is formed on the gate insulating film 8 to a thickness of 200 nm by the LPCVD method.
The amorphous silicon film 60 thus formed is covered with a photoresist film, and then the photoresist film is patterned by photolithography, X-ray lithography, or electron beam exposure. Subsequently, the amorphous silicon film 60 is etched by a reactive ion etching (RIE) method to form a gate electrode.
After forming the gate electrode, thin diffusion layers 16 and 28 serving as source-drain regions are formed in the n-type wells 16 and p-type wells 24, respectively, by an ion implantation method. Ion implantation is performed under normal conditions as in the second embodiment.
In the next step, a silicon nitride film is deposited on the entire surface of the P-type silicon semiconductor substrate 2A by the LPCVD method, and then anisotropically etches the silicon nitride film by the RIE method to act as a gate electrode. The gate sidewall film 14 is formed on the side surface of the gate sidewall. Subsequently, deep diffusion layers 18 and 30 serving as source-drain regions are formed in the n-type well 6 and the p-type well 24 by ion implantation methods. The ion implantation method is performed under ordinary conditions as in the second embodiment.
It should be noted that the heat treatment step should not be performed as much as possible after deposition of the amorphous silicon layer 60 so that the amorphous silicon film 60 is not deformed into the polycrystalline silicon film. 25 shows the final structure of the semiconductor device.
In the next step, the titanium layer 62 is deposited on the entire surface including the amorphous silicon film 60 by a sputtering method with a thickness of 40 nm, and then heat treated by RTA at a temperature of 700 ° C. for 30 seconds. . By this heat treatment, the titanium layer located on the amorphous silicon film 60 serving as the gate electrode and the deep diffusion regions 18 and 30 is transformed into a titanium silicide film. The unreacted titanium layer is then selectively removed by a selective removal method using a mixed solution of sulfuric acid and hydrogen peroxide. Thereafter, heat treatment is performed by RTA at 850 ° C. for 20 seconds. As a result, titanium silicide films 12 and 20 are selectively formed in each of the polycrystalline silicon film 10 and the deep diffusion layers 18 and 30 serving as gate electrodes. It should be noted that, by the second heat treatment by RTA, the amorphous silicon film 60 is transformed into a polycrystalline silicon film, and the dopants included in the deep diffusion layers 18 and 30 are activated.
It should be noted that since the gate electrode is formed of the above-described amorphous silicon film 60, the titanium silicide film 12 is formed at a high rate on the gate electrode composed of the amorphous silicon film 60. On the other hand, silicidation of the titanium layers disposed in the deep diffusion layers 18 and 30 is not promoted. Therefore, the titanium silicide film 20 is formed at a normal ratio. The titanium silicide film 12 disposed on the amorphous silicon film 60 is formed at least 1.2 times the same thickness as the titanium silicide film 20 disposed on the deep diffusion layers 18 and 30.
The semiconductor device of the salicide structure, which is the semiconductor device according to the first embodiment of the present invention shown in Fig. 4, is manufactured in accordance with the above-described steps. Incidentally, conventional manufacturing processes of MOS-FETs can be used in subsequent steps of manufacturing semiconductor devices.
As described above, according to the fifth embodiment of the present invention, since the gate electrode is formed of amorphous silicon, as a result, silicidation of the titanium layer disposed on the gate electrode is promoted. This makes it possible to fabricate a salicide-structured semiconductor device, in which the silicide film disposed on the gate electrode becomes relatively thicker than the silicide film disposed on the source-drain diffusion layer. More specifically, the silicide film disposed on the gate electrode is at least 1.2 times the same thickness as the silicide film formed on the source-drain diffusion layer.
In the fifth embodiment described above, each of the silicide film 12 included in the gate electrode and the silicide film 20 disposed on the source-drain diffusion layer is made of titanium silicide. However, these silicide films need not be limited to titanium silicide films. Specifically, these silicide films may be composed of silicides of metals having a high melting point such as cobalt or nickel.
In addition, the gate insulating film 8 is comprised with the silicon oxide film in 5th Example mentioned above. However, another insulating film such as a silicon nitride film or a silicon nitride oxide film can be used in place of the silicon oxide film for forming the gate insulating film 8. In addition, a p-type silicon semiconductor substrate is used in the fifth embodiment described above. However, it is also possible to use an n-type silicon semiconductor substrate.
(Example 6)
A sixth embodiment of the present invention relates to the manufacture of a semiconductor device having a salicide structure, which is a semiconductor device according to the first embodiment of the present invention shown in FIG. In the sixth embodiment, the silicide films 12 and 20 are composed of titanium silicide films as in the second embodiment. In addition, the silicon semiconductor substrate 2A used in the sixth embodiment is p-type conductivity.
28 to 32 are cross-sectional views showing in common a method of manufacturing a semiconductor device according to the sixth embodiment of the present invention. The sixth embodiment relates to the manufacture of a semiconductor device having a salicide structure, which is a semiconductor device according to the first embodiment of the present invention shown in FIG.
In the first step, the element isolation region 4 is formed on the p-type silicon semiconductor substrate 2A to a depth of about 300 nm by the buried element isolation method shown in FIG. 28 as in the second embodiment. A buffer oxide film is then formed to a thickness of about 10 nm on the surface of the p-type silicon semiconductor substrate 2A in the element formation region located between two adjacent element isolation regions 4.
After formation of the buffer oxide film, the n-type well 16, the p-type well 24, and the channel region are formed on the p-type silicon semiconductor substrate 2A by ion implantation into the element formation region. Ion implantation is performed under ordinary conditions as in the second embodiment. Subsequently, the buffer oxide film is removed, and then a gate insulating film 8 made of a silicon oxide film having a thickness of 2.5 nm to 6.0 nm is formed by a thermal oxidation method or an LPCVD method. In addition, a polycrystalline silicon film 10 serving as a gate electrode is formed on the gate insulating film 8 with a thickness of 200 nm by the LPCVD method.
The polycrystalline silicon film 10 thus formed is coated with photoresist, and then the photoresist film is patterned by photolithography, X-ray lithography or electron beam exposure. Thereafter, the polycrystalline silicon film 10 is etched by a reactive ion etching (RIE) method to form a gate electrode.
After formation of the gate electrode, thin diffusion layers 16 and 18 serving as source-drain regions are formed in each of the n-type wells 16 and p-type wells 24 by an ion implantation method. Ion implantation is carried out under ordinary conditions as in the second embodiment.
In the next step, a silicon nitride film is deposited on the entire surface of the P-type silicon semiconductor substrate 2A by the LPCVD method, and then anisotropically etches the silicon nitride film by the RIE method to act as a gate electrode. The gate sidewall film 14 is formed on the side surface of the gate sidewall. Subsequently, deep diffusion layers 18 and 30 serving as source-drain regions are formed in the n-type well 6 and the p-type well 24 by ion implantation methods. The ion implantation method is performed under ordinary conditions as in the second embodiment.
It should be noted that the impurity ions are implanted directly into the polycrystalline silicon film 10 serving as the gate electrode, whereby the gate electrode is doped to a high impurity concentration. Therefore, each of the polycrystalline silicon film 10 and the deep diffusion layers 18 and 30, which are doped by RTA by activation of an active annealing treatment and act as a gate electrode, is at least 1.0 × 10 ²⁰ cm ^-3. Will have an impurity concentration of.
In the next step, the titanium layer is deposited on the entire surface by a sputtering method with a thickness of 20 to 30 nm, followed by heat treatment by RTA at 700 ° C. for 30 seconds. By this heat treatment, the titanium layer disposed on the polycrystalline silicon film 10 and the deep diffusion layers 18 and 30 serving as the gate electrode is transformed into a titanium silicide film. The unreacted titanium layer is then selectively removed by a selective removal method using a mixed solution consisting of sulfuric acid and hydrogen peroxide. Thereafter, heat treatment is performed by RTA at 850 ° C. for 20 seconds. As a result, titanium silicide films 70 and 20 are selectively formed in each of the polycrystalline silicon film 10 and the deep diffusion layers 18 and 30 serving as gate electrodes.
Titanium silicide films 70 and 20 having substantially the same thickness as each other are formed on the polycrystalline silicon film 10 and the deep diffusion layers 18 and 30 serving as gate electrodes by the general method of manufacturing the salicide structure described above. Is formed. It should be noted, however, that the titanium layer deposited on the polycrystalline silicon film 10 and the deep diffusion layers 18 and 30 is thinner than that formed in the other embodiments described above. As a result, the titanium silicide films 70 and 20 formed in the sixth embodiment are thinner than the titanium silicide films formed in the other embodiments described above. 28 shows the final structure of the semiconductor device.
In the next step, as shown in Fig. 29, for example, an insulating film 72 made of BPSG is deposited on the entire surface of the p-type silicon semiconductor substrate 2A with a thickness of about 600 nm by the LPCVD method. Next, after the surface of the insulating film 72 is flattened by a chemical mechanical polishing (CMP) method, the insulating film is etched back by CMP or RIE using the polycrystalline silicon film 10 as a stopper, as shown in FIG. 30. Only the surface of the titanium silicide film 70 is selectively exposed.
Next, as shown in FIG. 31, the titanium layer 74 is deposited by the sputtering method to a thickness of 40 nm, and then heat-processed by RTA at 700 degreeC for 30 second. By this heat treatment, the titanium layer disposed on the titanium silicide film 70 formed on the polycrystalline silicon film 10 is transformed into a titanium silicide layer. Subsequently, the unreacted titanium layer is selectively removed by a selective removal method using a mixed solution of sulfuric acid and hydrogen peroxide as shown in FIG. 32, followed by heat treatment by RTA at 850 ° C. for 20 seconds. . As a result, a titanium silicide film 12 is further formed on the titanium silicide film 70.
As described above, an additional titanium silicide film is selectively formed on the titanium silicide film 70, which is placed on the polycrystalline silicon film 10 serving as the gate electrode. Thereafter, the titanium silicide film 12 disposed on the polycrystalline silicon film 10 is formed at least 1.2 times the same thickness as the titanium silicide film 20 disposed on the deep diffusion layers 18 and 30.
A semiconductor device having a salicide structure, which is a semiconductor device according to the first embodiment of the present invention shown in Fig. 4, is manufactured in accordance with the above-described steps. In this regard, conventional methods of manufacturing MOS-FETs can be used in subsequent steps of manufacturing semiconductor devices.
As described above, according to the sixth embodiment of the present invention, after the salicide structure is manufactured by a conventional manufacturing method, the surface of the silicide film disposed on the gate electrode is selectively exposed while the other region is covered with the insulating film. . Under these conditions, the silicide film is formed narrow on the silicide film disposed on the gate electrode. Thereafter, it is possible to manufacture a salicide-structured semiconductor device, in which the silicide film disposed on the gate electrode is formed relatively thicker than the silicide film disposed on the source-drain diffusion layer. Note that the silicide film disposed on the gate electrode is formed at least 1.2 times the same thickness as the silicide film disposed on the source-drain diffusion layer.
In the sixth embodiment described above, each of the silicide film 12 included in the gate electrode and the silicide film 20 disposed on the source-drain diffusion layer is made of titanium silicide. However, these silicide films need not be limited to titanium silicide films. Specifically, these silicide films may be composed of silicides of metals having a high melting point such as cobalt or nickel.
Note that the gate insulating film 8 is composed of a silicon oxide film in the sixth embodiment described above. However, another insulating film such as a silicon nitride film or a silicon nitride oxide film can be used in place of the silicon oxide film for forming the gate insulating film 8. In addition, a p-type silicon semiconductor substrate is used in the fifth embodiment described above. However, it is also possible to use an n-type silicon semiconductor substrate.
As described above, it is necessary to reduce the gate delay time in order to achieve high speed operation in the semiconductor device of the MIS structure having the silicide structure. In order to achieve another object, it is absolutely necessary to reduce the resistance of the gate electrode. To this end, it is necessary to reduce the sheet resistance of the silicide film located on the gate electrode. Therefore, it is necessary to increase the thickness of the silicide film located on the gate electrode.
On the other hand, in the case of forming a silicide film having a normal thickness or a silicide film thicker than the conventional silicide film, it is necessary to form a source-drain diffusion layer constituting a deep junction to prevent current leakage at the junction of the source-drain diffusion layer. have. As a result, occurrence of a short channel effect is remarkable, which hinders miniaturization of the semiconductor device.
In this regard, it should be noted that in the silicide film positioned in the source-drain diffusion layer, the sheet resistance of the silicide film occupies a small ratio compared to the overall parasitic capacitance, so that the silicide film is used in the conventional semiconductor device to miniaturize the semiconductor device. It is not a problem even if it is formed thinner than the silicide film.
On the other hand, by the method of the present invention, it is possible to form a silicide film on the gate electrode thicker than that used in the conventional device, and to form the silicide film in the source-drain diffusion layer thinner than that used in the conventional device. That is, the two problems inherent in the conventional method can be solved by the method of the present invention. Specifically, by the method of the present invention, it is possible to increase the thickness of the silicide film located on the gate electrode and at the same time reduce the thickness of the silicide film located on the source-drain diffusion layer.
In other words, the present invention provides a semiconductor device including a MIS transistor having a salicide structure, wherein the silicide film disposed on the gate electrode is formed at least 1.2 times the same thickness as the silicide film disposed on the source-drain diffusion layer in the semiconductor device. Is that. Certain semiconductor devices of the present invention can be miniaturized and operated at high speed. The invention also provides a method of manufacturing a particular semiconductor device.
As described above, the present invention relates to a device having a salicide structure, wherein the silicide film disposed on the gate electrode is made thicker than the silicide film disposed on the source-drain diffusion layer to miniaturize the semiconductor device and achieve high speed operation. Provide a device.
The present invention also provides a method of manufacturing a semiconductor device having a salicide structure in which a silicide film disposed on a gate electrode is made thicker than a silicide film disposed in a source-drain diffusion layer.
Additional advantages and modifications may be considered to those skilled in the art. Accordingly, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

权利要求:
Claims (17)
[1" claim-type="Currently amended] In a semiconductor device,
A source-drain diffusion layer formed on the semiconductor substrate;
A first silicide layer formed on the source-drain diffusion layer;
A gate electrode formed on the gate insulating film disposed on the semiconductor substrate; And
A second silicide film disposed on the gate electrode and thicker than the first silicide film
Semiconductor device comprising a.
[2" claim-type="Currently amended] The semiconductor device of claim 1, wherein the second silicide film formed on the gate electrode is at least 1.2 times thicker than the first silicide film formed on the source-drain diffusion layer.
[3" claim-type="Currently amended] The semiconductor device according to claim 1, wherein a gate sidewall film is formed on the side of said gate electrode.
[4" claim-type="Currently amended] The semiconductor device of claim 1, wherein the source-drain diffusion layer comprises a shallow diffusion layer and a deep diffusion layer to form a lightly doped drain (LDD) structure.
[5" claim-type="Currently amended] The semiconductor device according to claim 1, wherein said gate electrode is composed of a polycrystalline silicon film.
[6" claim-type="Currently amended] In the method of manufacturing a semiconductor device,
Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a source-drain diffusion layer on the semiconductor substrate;
Selectively introducing atoms to inhibit silicidation into the source-drain diffusion layer;
Forming a metal film having a high melting point on the gate electrode and the source-drain diffusion layer; And
Converting the high melting point metal film into a silicide film to selectively form a silicide film on the gate electrode and the source-drain diffusion layer
A semiconductor device manufacturing method comprising a.
[7" claim-type="Currently amended] The method of claim 6, wherein the atoms that serve to inhibit the suicide are selected from the group consisting of fluorine, nitrogen, and oxygen.
[8" claim-type="Currently amended] The method of claim 6, wherein the atoms serving to inhibit the suicide are introduced into the source-drain diffusion layer by ion implantation.
[9" claim-type="Currently amended] In the method of manufacturing a semiconductor device,
Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a source-drain diffusion layer on the semiconductor substrate;
Forming a film on the source-drain diffusion layer that inhibits suicideization;
Forming a metal film having a high melting point on the gate electrode and the source-drain diffusion layer; And
Converting the high melting point metal film into a silicide film to selectively form a silicide film on the gate electrode and the source-drain diffusion layer
A semiconductor device manufacturing method comprising a.
[10" claim-type="Currently amended] 10. The method of claim 9, wherein the film serving to suppress the suicide is selected from the group consisting of an oxide film and a nitride film.
[11" claim-type="Currently amended] In the method of manufacturing a semiconductor device,
Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a source-drain diffusion layer on the semiconductor substrate;
Forming an insulating film on the gate electrode and the source-drain diffusion layer;
Thinning the insulating film to expose the surface of the gate electrode while maintaining the source-drain diffusion layer covered with the insulating film;
Introducing atoms into an area near the surface of the gate electrode such that an upper portion of the gate electrode is amorphous;
Removing an insulating film disposed on the source-drain diffusion layer;
Forming a metal film having a high melting point on the gate electrode and the source-drain diffusion layer; And
Converting the high melting point metal film into a silicide film to selectively form a silicide film on the gate electrode and the source-drain diffusion layer
A semiconductor device manufacturing method comprising a.
[12" claim-type="Currently amended] The method of claim 11, wherein the atoms introduced to the surface region of the gate electrode are selected from the group consisting of boron, germanium, silicon, arsenic, and antimony.
[13" claim-type="Currently amended] The method of claim 11, wherein the atoms are introduced into the surface region of the gate electrode by ion implantation.
[14" claim-type="Currently amended] In the method of manufacturing a semiconductor device,
Forming a gate insulating film on the semiconductor substrate;
Forming an amorphous silicon film having a form of a gate electrode on the gate insulating film;
Forming a source-drain diffusion layer on the semiconductor substrate;
Forming a metal film having a high melting point on the amorphous silicon film and the source-drain diffusion layer; And
Converting the high melting point metal film into a silicide film to selectively form a silicide film on the amorphous silicon film and the source-drain diffusion layer
A semiconductor device manufacturing method comprising a.
[15" claim-type="Currently amended] 15. The method of claim 14, wherein the forming of the silicide film comprises a heat treatment for converting the high melting point metal film into a silicide film, wherein the amorphous silicon film is converted into a polycrystalline silicon film by the heat treatment. .
[16" claim-type="Currently amended] In the method of manufacturing a semiconductor device,
Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a source-drain diffusion layer on the semiconductor substrate;
Selectively forming a silicide layer on the gate electrode and the source-drain diffusion layer;
Forming an insulating film on the silicide film disposed on the gate electrode and the source-drain diffusion layer;
Thinning the insulating film to expose a surface of the silicide film disposed on the gate electrode while keeping the silicide film disposed on the source-drain diffusion layer covered with the insulating film; And
Further forming a silicide film on the exposed silicide film surface
A semiconductor device manufacturing method comprising a.
[17" claim-type="Currently amended] In the method of manufacturing a semiconductor device,
Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a source-drain diffusion layer on the semiconductor substrate;
Forming a metal film having a high melting point on the gate electrode and the source-drain diffusion layer;
Converting the high melting point metal film into a silicide film to selectively form a silicide film on the gate electrode and the source-drain diffusion layer;
Forming an insulating film on the silicide film disposed on the gate electrode and the source-drain diffusion layer;
Thinning the insulating film to expose a surface of the silicide film disposed on the gate electrode while keeping the silicide film disposed on the source-drain diffusion layer covered with the insulating film;
Forming a high melting point metal film on the silicide film disposed on the gate electrode; And
Converting the high melting point metal film into a silicide film to selectively form a silicide film on the silicide film previously formed on the gate electrode
A semiconductor device manufacturing method comprising a.

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TW401585B|2000-08-11|

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1997-10-01|Priority to JP97-268513

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1997-10-01|Priority to JP26851397A

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1998-09-30|Application filed by 니시무로 타이죠, 가부시끼가이샤 도시바

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1999-05-25|Publication of KR19990036745A

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2002-11-18|Application granted

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2002-11-18|Publication of KR100352758B1

优先权:

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申请号 | 申请日 | 专利标题

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JP97-268513|1997-10-01|

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JP26851397A|JP3389075B2|1997-10-01|1997-10-01|Method for manufacturing semiconductor device|